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precision rail - to - rail input and output operational ampli fiers op184/op284/op484 rev. j information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 1996 C 2011 analog devices, inc. all rights reserved. features single - supply operation wide bandwidth: 4 mhz low offset voltage: 65 v unity - gain stable high slew rate: 4.0 v/ s low noise: 3.9 nv/ hz applications battery - powered instrumentation power supply control and protection telecom munications dac output amplifier adc input buffer general description the op184 / op284 / op484 are single, dual, and quad single - supply, 4 mhz bandwidth amplifiers featuring rail - to - rail inputs and outputs. they are guaranteed to operate from 3 v to 36 v (or 1.5 v to 18 v). thes e amplifiers are superb for single - supply applications requiring both ac and precision dc performance. the combination of wide bandwidth, low noise, and precision makes the op184 / op284 / op484 useful in a wide variety of applications, including filters and instrumentation. other applications for these amplifiers include portable telecom - munications equipment, power supply control and protection, and use as amplifiers or buffers for transducers with wide output ranges. sensors requiring a rail - to - rail input ampli fier include hall effect, piezoelectric, and resistive transducers. the ability to swing rail - to - rail at both the input and output enables designers to build multistage filters in single -supply systems and to maintain high signal - to - noise ratios. the op184 / op284 / op484 are specified ov er the hot extended industrial temperature range of ?40c to +125c . the single op184 is available in 8 - lead soic surface mount packages. the dual op284 is available in 8 - lead pdip and soic surface mount packages. the quad op484 is available in 14 - lead pdip and 14- lead, narrow - body soic packages. pin configurations 1 2 3 4 out a v+ dnc nc dnc ?in a +in a v? 8 7 6 5 notes 1. nc = no connect 2. dnc = do not connect ? + 00293-001 top view (not to scale) op184 figure 1. 8 - lead soic (s - suffix) 00293-002 1 2 3 4 8 7 6 5 out b ?in b +in b v+ out a ?in a +in a v? op284 top view (not to scale) figure 2. 8 - lead pdip (p - suffix) 8- lead soic (s - suffix) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 out a ?in a +in a v+ +in b ?in b out b out d ?in d +in d v? +in c ?in c out c op484 top view (not to scale) 00293-003 figure 3 . 14 - lead pdip (p - suffix) 14 - lead narrow - body soic (s - suffix) table 1 . low noise op amps voltage noise 0.9 nv 1.1 nv 1.8 nv 2.8 nv 3.2 nv 3.8 nv 3.9 nv single ad797 ad8597 ada4004 -1 ad8675 / ada4075 -2 op27 ad8671 op184 dual ad8599 ada4004 -2 ad8676 op270 ad8672 op284 quad ada4004 -4 op470 ad8674 op484
op184/op284/op484 rev. j | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 pin configurations ........................................................................... 1 revision history ............................................................................... 2 sp ecifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 typical performance characteristics ............................................. 7 applications information .............................................................. 14 functional description .............................................................. 14 input overvoltage protection ................................................... 14 output phase reversal ............................................................... 15 designing low noise circuits in single - supply applications ....................................................................................................... 15 ove rdrive recovery ................................................................... 16 single - supply, 3 v instrumentation amplifier ...................... 16 2.5 v reference from a 3 v supply .......................................... 17 5 v only, 12 - bit dac swings rail - to - rail ............................. 17 high - side current monitor ...................................................... 18 capacitive load drive capability ............................................ 18 low dropout regulator with current limiting ..................... 19 3 v, 50 hz/60 hz active notch filter with false ground ..... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 23 revision history 4 /1 1 rev. i to rev j change to figure 27 ....................................................................... 10 10/10 rev. h to rev i change to output characteristics, output voltage high parameter, table 2 ............................................................................. 3 change to output characteristics, output voltage high parameter, table 3 ............................................................................. 4 7/10 rev. g to rev. h added table 1 .................................................................................... 1 2 /09 rev. f to rev. g change to larg e signal voltage gain, table 3 .............................. 5 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 22 9 /08 rev. e to rev. f changes to general description .................................................... 1 changes to figure 4 .......................................................................... 6 changes to low dropout regulator with current limiting .... 20 7/08 rev. d to rev. e changes to figure 1 .......................................................................... 1 changes to figure 12 ........................................................................ 8 changes to figure 36 and figure 37 ............................................. 12 changes to designing low nois e circuits in single - supply applications section ....................................................................... 15 updated outline dimensions ....................................................... 21 c hanges to ordering guide .......................................................... 22 4/06 rev. c to rev. d changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 changes to table 3 ............................................................................. 5 deleted reference to 1993 system applications guide .............. 15 3/06 rev. b to rev. c changes to figure 1 caption ............................................................ 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 changes to table 3 ............................................................................. 5 changes to table 4 ............................................................................. 6 changes to figure 5 through figure 9 ............................................ 7 changes to functional description section ............................... 14 deleted spice macro model ........................................................ 21 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 22 9/02 rev. a to rev. b changes to pin configurations ....................................................... 1 changes to specifications, input bias current max imum .......... 2 changes to ordering guide ............................................................. 5 updated outline dimensions ....................................................... 19 6/02 rev. 0 to rev. a 10/96 revision 0: initial version
op184/op284/op484 rev. j | page 3 of 24 specifications electrical character istics v s = 5.0 v, v cm = 2.5 v, t a = 25c, unless otherwise noted. table 2 . parameter symbol conditions min typ max unit input characteristics offset voltage, op184/op284e grade 1 v os 65 v ? 40c t a +125c 165 v offset voltage, op184/op284f grade 1 v os 125 v ? 40c t a +125c 350 v offset voltage, op484e grade 1 v os 75 v C 40c t a +125c 175 v offset voltage, op484f grade 1 v os 150 v C 40c t a +125c 450 v input bias current i b 60 450 na C 40c t a +125c 600 na input offset current i os 2 50 na C 40c t a +125c 50 na input voltage range 0 5 v common - mode rejection ratio cmrr v cm = 0 v to 5 v 60 db v cm = 1.0 v to 4.0 v, ?40c t a +125c 86 db large signal voltage gain a vo r l = 2 k ?, 1 v v o 4 v 50 240 v/mv r l = 2 k ?, ?40c t a +125c 25 v/mv bias current drift i b / t 150 pa/c output characteristics output voltage high v oh i l = 1.0 ma 4.8 0 v output voltage low v ol i l = 1.0 ma 125 mv output current i out 6.5 ma power supp ly power supply rejection ratio psrr v s = 2.0 v to 10 v, ?40c t a +125c 76 db supply current/amplifier i sy v o = 2.5 v, ?40c t a +125c 1.45 ma supply voltage range v s 3 36 v dynamic performance slew rate sr r l = 2 k ? 1.65 2.4 v/s settling time t s to 0.01%, 1.0 v step 2.5 s gain bandwidth product gbp 3.25 mhz phase margin m 45 degrees noise performance voltage noise e n p- p 0.1 hz to 10 hz 0.3 v p -p voltage nois e density e n f = 1 khz 3.9 nv/ hz current noise density i n 0.4 pa/ hz 1 input offset v oltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
op184/op284/op484 rev. j | page 4 of 24 v s = 3.0 v, v cm = 1.5 v, t a = 25c, unless otherwise noted. table 3 . parameter symbol conditions min typ max unit input characteristics offs et voltage, op184/op284e grade 1 v os 65 v ? 40c t a +125c 165 v offset voltage, op184/op284f grade 1 v os 125 v ? 40c t a +125c 350 v offset voltage, op484e grade 1 v os 100 v C 40c t a +125c 200 v offset voltage, op484f grade 1 v os 150 v C 40c t a +125c 450 v input bias current i b 60 450 na ? 40c t a +125c 600 na input offse t current i os ? 40c t a +125c 50 na input voltage range 0 3 v common - mode rejection ratio cmrr v cm = 0 v to 3 v 60 db v cm = 0 v to 3 v, ?40c t a +125c 56 db output characteristics output voltage high v oh i l = 1.0 ma 2.80 v output voltage low v ol i l = 1.0 ma 125 mv power supply power supply rejection ratio psrr v s = 1.25 v to 1.75 v 76 db supply current/amplifier i sy v o = 1.5 v, ?40c t a +125c 1.35 ma dynamic performance gain bandwidth product gbp 3 mhz noise performance voltage noise density e n f = 1 khz 3.9 nv/ hz 1 in put offset v oltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
op184/op284/op484 rev. j | page 5 of 24 v s = 15.0 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 4. parameter symbol conditions min typ max u nit input characteristics offset voltage, op184/op284e grade 1 v os 100 v ? 40c t a +125c 200 v offset voltage, op184/op284f grade 1 v os 175 v ? 40c t a +125c 375 v offset voltag e, op484e grade 1 v os 150 v ? 40c t a +125c 300 v offset voltage, op484f grade 1 v os 250 v ? 40c t a +125c 500 v input bias current i b 80 450 na ? 40c t a +125c 575 na input offset current i os ? 40c t a +125c 50 na input voltage range ?15 +15 v common - mode rejection ratio cmrr v cm = ?14.0 v to +14.0 v, ?40c t a +125c 86 90 db v cm = ?15.0 v to +15.0 v 80 db large s ignal voltage gain a vo r l = 2 k ?, ?10 v v o 10 v 150 1000 v/mv r l = 2 k?, ?40c t a +125c 75 v/mv offset voltage drift e grade v os / t 0.2 2.00 v/c bias current drift v b / t 150 pa/c output characteristics output voltage high v oh i l = 1.0 ma 14.8 v output voltage low v ol i l = 1.0 ma ? 14.875 v output current i out 10 ma power supply power supply rejection ratio psrr v s = 2.0 v to 18 v, ?40c t a +125c 90 db supply current/amplifier i sy v o = 0 v, ?40c t a +125c 2.0 ma supply current/amplifier i sy v s = 18 v, ?40c t a +125c 2.25 ma dynamic performance slew rate sr r l = 2 k ? 2.4 4.0 v/s full - power bandwidth bw p 1% distortion, r l = 2 k ?, v o = 29 v p-p 35 khz settling time t s to 0.01%, 10 v step 4 s gain bandwidth product gbp 4.25 mhz phase margin m 50 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 0.3 v p -p voltage noise density e n f = 1 khz 3.9 n v/ hz current noise density i n 0.4 pa/ hz 1 input offset v oltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power .
op184/op284/op484 rev. j | page 6 of 24 absolute maximum rat ings table 5 . parameter rating supply voltage 18 v input voltage 18 v differential input voltage 1 0.6 v output short - circuit duration to gnd indefinite storage temperature range p- suffix, s - suffix packages ?65c to +150c operating temperature range op184/op284/op484e/op484f ?40c to +125c junction temperature range p- suffix, s - suffix packages ?65c to +150c lead temperature (soldering 60 sec ) 300c 1 for input voltages greater than 0.6 v, the input current should be limited to less than 5 ma to prevent degradation or destruction of the input devices. stresses above those listed under absolute maximum ratings may cause permanent damage to th e device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended p eriods may affect device reliability. absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. thermal resistance ja is specified for the worst - case conditions; that is, ja is specified for a device in socket for pdip. ja is specified for a device soldered in the circuit board for soic packages. table 6 . thermal resistance package type ja jc unit 8- lead pdip (p - suffix) 103 43 c/w 8- lead soic (s - suffix) 158 43 c/w 14- lead pdip (p - suffix) 83 39 c/w 14- lead soic (s - suffix) 92 27 c/w esd caution r3 q1 ?in +in ql1 ql2 q4 q3 q2 qb5 qb6 rb2 qb3 r1 q5 r2 qb4 jb2 qb1 n+cb1 p+m qb2 cc1 q9 q7 q11 q8 q6 q10 q12 qb7 qb8 qb9 rb1 jb1 tp r4 r5 r6 rb3 ff c r7 r8 q13 q14 r10 q15 rb4 qb10 cc2 c o q17 q16 r11 q18 v cc out v ee r9 00293-004 figure 4 . simplified schematic
op184/op284/op484 rev. j | page 7 of 24 typical performance characteristics input offset voltage (v) quantity 300 0 270 180 90 60 30 240 210 120 150 ?100 ?75 ?50 ?25 0 25 50 75 100 00293-005 v s = 3v t a = 25c v cm = 1.5v figure 5 . input offset voltage distribution 00293-006 input offset voltage (v) quantity 300 0 270 180 90 60 30 240 210 120 150 ?100 ?75 ?50 ?25 0 25 50 75 100 v s = 5v t a = 25c v cm = 2.5v figure 6 . input offset voltage distribution 00293-007 input offset voltage (v) quantity 200 0 175 100 75 50 25 150 125 ?125 ?100 ?75 ?50 ?25 0 25 100 50 75 125 v s = 15v t a = 25c figure 7 . input offset voltage distribution 300 250 200 150 100 50 0 0 0.25 0.50 0.75 1.00 1.25 1.50 quantity offset voltage drift, tcv os (v/c) 00293-008 v s = 5v ?40c t a +125c figure 8 . input offset voltage drift distribution 300 250 200 150 100 50 0 0 0.25 0.50 0.75 1.00 1.25 1.50 quantity offset voltage drift, tcv os (v/c) 00293-009 v s = 15v ?40c t a +125c figure 9 . input o ffset voltage drift distribution ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?40 25 85 125 v cm = v s /2 v s = +5v v s = 15v input bias current (na) temperature (c) 00293-010 figure 10 . bias current vs. temperature
op184/op284/op484 rev. j | page 8 of 24 500 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 ?15 ?10 ?5 0 5 10 15 input bias current (na) common-mode voltage (v) 00293-011 v s = 15v figure 11 . input bias current vs. common - mode voltage 1000 10 100 0.01 0.1 1 10 output voltage (mv) load current (ma) 00293-012 source sink v s = 15v figure 12 . output voltage to supply rail v s. load current 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 ?40 25 85 125 supply current/amplifier (ma) temperature (c) 00293-013 v s = 15v v s = +5v v s = +3v figure 13 . supply current vs. temperature 1.50 1.25 1.00 0.75 0.50 0.25 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 supply current/per amplifier (ma) supply voltage (v) 00293-014 t a = 25c figure 14 . supply current vs. supply voltage 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 short-circuit current (ma) temperature (c) 00293-015 v s = 15v +i sc ?i sc +i sc ?i sc v s = +5v, v cm = +2.5v figure 15 . short - circuit current vs. temperature 70 60 50 40 30 20 10 0 ?10 ?20 ?30 0 45 90 135 180 225 270 10k 100k 1m 10m open-loop gain (db) phase shift (degrees) frequency (hz) 00293-016 v s = 5v t a = 25c no load figure 16 . open - loop gain and phase vs. frequency (no load)
op184/op284/op484 rev. j | page 9 of 24 70 60 50 40 30 20 10 0 ?10 ?20 ?30 0 45 90 135 180 225 270 10k 100k 1m 10m open-loop gain (db) phase shift (degrees) frequency (hz) 00293-017 v s = 3v t a = 25c no load figure 17 . open - loop gain and phase vs. frequency (no load) 70 60 50 40 30 20 10 0 ?10 ?20 ?30 0 45 90 135 180 225 270 10k 100k 1m 10m open-loop gain (db) phase shift (degrees) frequency (hz) 00293-018 v s = 15v t a = 25c no load figure 18 . open - loop gain and phase vs. frequency (no load) 2500 2000 1500 1000 500 0 ?50 125 100 75 50 25 0 ?25 open-loop gain (v/mv) temperature (c) 00293-019 v s = 15v ?10v < v o < +10v r l = 2k ? v s = +5v +1v < v o < +10v r l = 2k ? fi gure 19 . open - loop gain vs. temperature 60 50 40 30 20 10 0 ?10 ?20 ?40 ?30 10 1k 100k 10m 100 10k 1m closed-loop gain (db) frequency (hz) 00293-020 v s = 5v r l = 2k ? t a = 25c figure 20 . closed - loop gain vs. frequency (2 k ? load) 60 50 40 30 20 10 0 ?10 ?20 ?40 ?30 10 1k 100k 10m 100 10k 1m closed-loop gain (db) frequency (hz) 00293-020 v s = 15v r l = 2k ? t a = 25c figure 21 . closed - loop gain vs. frequency (2 k ? load) 60 50 40 30 20 10 0 ?10 ?20 ?40 ?30 10 1k 100k 10m 100 10k 1m closed-loop gain (db) frequency (hz) 00293-020 v s = 3v r l = 2k ? t a = 25c figure 22 . closed - loop gain vs. frequency (2 k ? load)
op184/op284/op484 rev. j | page 10 of 24 300 270 240 210 180 150 120 90 60 0 30 10 1k 100k 10m 100 10k 1m output impedance ( ?) frequency (hz) 00293-023 v s = 5v t a = 25c a v = +100 a v = +10 a v = +1 figure 23 . outpu t impedance vs. frequency 300 270 240 210 180 150 120 90 60 0 30 10 1k 100k 10m 100 10k 1m output impedance ( ?) frequency (hz) 00293-024 v s = 15v t a = 25c a v = +100 a v = +10 a v = +1 figure 24 . output impedance vs. frequency 300 270 240 210 180 150 120 90 60 0 30 10 1k 100k 10m 100 10k 1m output impedance ( ?) frequency (hz) 00293-025 v s = 3v t a = 25c a v = +100 a v = +10 a v = +1 figure 25 . output impedance vs. frequency 5 4 3 2 1 0 1k 100k 10m 10k 1m maximum output swing (v p-p) frequency (hz) 00293-026 v s = 5v v in = 0.5v to 4.5v r l = 2k ? t a = 25c figure 26 . maximum output swing vs. frequency 30 25 20 15 10 5 0 1k 100k 10m 10k 1m vout (v) frequency (hz) 00293-027 v s = 15v v in = 14v r l = 2k ? t a = 25c figure 27 . maximum output swing vs. frequency 180 160 140 120 100 80 60 40 20 0 ?20 10 100k 10m 1k 100 10k 1m cmrr (db) frequency (hz) 00293-028 v s = 15v v s = +5v v s = +3v t a = 25c figure 28 . cmrr vs. frequency
op184/op284/op484 rev. j | page 11 of 24 160 140 120 100 80 60 40 20 0 ?40 ?20 10 100k 10m 1k 100 10k 1m psrr (db) frequency (hz) 00293-029 v s = 15v v s = +5v v s = +3v t a = 25c figure 29 . psrr vs. frequency 80 70 60 50 40 30 20 10 0 10 1000 100 overshoot (%) capacitive load (pf) 00293-030 +os ?os v s = 2.5v t a = 25c, a vcl = 1 v in = 50mv figure 30 . small signal overshoot vs. capacitive load 7 6 5 4 3 2 1 0 ?50 ?25 0 25 50 75 100 125 slew rate (v/s) temperature (c) 00293-031 v s = 15v r l = 2k ? v s = 5v r l = 2k ? +slew rate ?slew rate +slew rate ?slew rate figure 31 . slew rate vs. temperature 30 25 20 15 10 5 0 1 10 100 1000 noise density (nv/ hz) frequency (hz) 00293-032 2.5v v s 15v t a = 25c figure 32 . voltage noise density vs. frequency 10 8 6 4 2 0 1 10 100 1000 current noise density (pa/ hz) frequency (hz) 00293-033 2.5v v s 15v t a = 25c figure 33 . current noise density vs. frequency 5 4 3 2 1 ?5 ?4 ?3 ?2 ?1 0 0 6 5 4 3 2 1 step size (v) settling time (s) 00293-034 v s = 5v t a = 25c 0.1% 0.01% figure 34 . step size vs. settling time
op184/op284/op484 rev. j | page 12 of 24 10 8 6 4 2 ?10 ?8 ?6 ?4 ?2 0 0 6 5 4 3 2 1 step size (v) settling time (s) 00293-035 v s = 15v t a = 25c 0.1% 0.01% figure 35 . step size vs. settling time 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 time noise (v) 00293-036 v s = 2.5v a v = 10m figure 36 . 0.1 hz to 10 hz noise 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 time noise (v) 00293-037 v s = 15v a v = 10m figure 37 . 0.1 hz to 10 hz noise 160 140 120 100 80 ?40 ?20 0 20 40 60 100 10m 1m 100k 10k 1k channel separation (db) frequency (hz) 00293-038 t a = 25c v s = 15v v s = +3v figure 38 . channel separation vs. frequency 00293-039 v s = 5v a v = +1 r l = open c l = 300pf t a = 25c 1s 100 90 10 0% 100mv 400mv 0v figure 39 . small signal transient response 00293-040 v s = 5v a v = +1 r l = 2k ? c l = 300pf t a = 25c 1s 100 90 10 0% 100mv 400mv 0v figure 40 . small signal transient response
op184/op284/op484 rev. j | page 13 of 24 00293-041 v s = 1.5v a v = +1 no load t a = 25c 500ns 100 90 10 0% 100mv +200mv 0v ?200mv figure 41 . small signal transient r esponse 00293-042 v s = 0.75v a v = +1 no load t a = 25c 1s 100 90 10 0% 100mv +200mv 0v ?200mv figure 42 . small signal transient response 0.1 0.0005 0.001 0.01 20 1k 20k 100 10k thd+n (%) frequency (hz) 00293-043 v o = 0.75v v o = 2.5v v o = 1.5v a v = +1000 v s = 2.5v r l = 2k ? figure 43 . total harmonic distortion + noise vs. frequency
op184/op284/op484 rev. j | page 14 of 24 applications informa tion functional descripti on the op184/op284/op484 are precis ion single - supply, rail - to - rail operational amplifiers. intended for the portable instrumentation marketplace, the opx84 family of devices combine the attributes of precision, wide bandwidth, and low noise to make them a superb choice in single - supply appl ications that require both ac and precision dc performance. other low supply voltage appli - cations for which the op284 is well suited are active filters, audio microphone preamplifiers, power supply control, and telecommunications. to combine all of these attributes with rail - to - rail input/output operation, novel circuit design techniques are used. d1 d2 q4 v+ i1 q3 2q 1q i2 v 01 v 02 ?i n x v? +in x 00293-044 ? ? r4 3k? r3 3k? r2 4k? r1 4k? figure 44 . op284 equivalent input circuit for example, figure 44 illustrates a simplified equivalent circui t for the input stage of the op184/op284/op484. it comprises an npn differential pair, q1q2, and a pnp differential pair, q3 q4, operating concurrently. diode network d1diode network d2 serves to clamp the applied differential input voltage to the op284, thereby protecting the input transistors against avalanche damage. input stage voltage gains are kept low for input rail - to - rail operation. the two pairs of differential outpu t voltages are connected to the second stage of the op284 , which is a compound folded cascade gain stage. it is also in the second gain stage, where the two pairs of di fferential output voltages are combined into a single - ended, output signal voltage used to drive the output stage. a key issue in the input stage is the behavior of the input bias currents over the input common - mode voltage range. input bias currents in th e op284 are the arithmetic sum of the base currents in q1 q3 and in q2q4. as a result of this design approach, the input bias currents in the op284 not only exhibit different amplitudes; they also exhibit different polarities. this effect is best illustra ted by figure 10 . it is, therefore, of paramount importance that the effective source impedances connected to the op284 inputs be balanced for optimum dc and ac performance. to achieve rail - to - rail output, the op284 output stag e design employs a unique topology for both sourcing and sinking current. this circuit topology is illustrated in figure 45 . the output stage is voltage - driven from the second gain stage. the signal path through the output stage is inverting; that is, for positive input signals, q1 provides the base current drive to q6 so that it conducts (sinks) current. for negative input signals, the signal path via q1 q2d1q4q3 provides the base current drive for q5 to conduct (source) curr ent. both amplifiers provide output current until they are forced into saturation, which occurs at approxi - mately 20 mv from the negative supply rail and 100 mv from the positive supply rail. 00293-045 v+ i2 i1 q1 q3 q4 q2 v? q5 v out q6 r6 r3 r2 r1 r4 r5 d1 input from second gain stage figure 45 . op284 equivalent output ci rcuit thus, the saturation voltage of the output transistors sets the limit on the op284 maximum output voltage swing. output short - circuit current limiting is determined by the maximum signal current into the base of q1 from the second gain stage. under o utput short - circuit conditions, this input current level is approximately 100 a . with transistor current gains around 200, the short - circuit current limits are typically 20 ma. the output stage also exhibits voltage gain. this is accomplished by the use of common - emitter amplifiers, and, as a result, the voltage gain of the output stage (thus, the open - loop gain of the device) exhibits a dependence to the total load resistance at the output of the op284. input overvoltage pr otection as with any semiconduc tor device, if conditions exist where the applied input voltages to the device exceed either supply voltage, the input overvoltage i - v characteristic of the device must be considered. when an overvoltage occurs, the amplifier could be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current. figure 46 illustrates the overvoltage i - v characteristic of the op284. this graph was generated with the supply pins connected to gnd and a curve tra ce rs collector output drive connected to the input.
op184/op284/op484 rev. j | page 15 of 24 00293-046 5 4 ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 input current (ma) input voltage (v) figure 46 . input overvoltage i - v characteristics of the op284 as shown in figure 46 , internal p - n junctions to the op284 energize and permit current flow from the inputs to the supplies when the input is 1.8 v more positive and 0.6 v more negative than the respective supply rails. as illustrated in the simplified equivalent circuit shown in figure 44 , the op284 does not have any intern al current limiting resistors; thus, fault currents can quickly rise to damaging levels. this input current is not inherently damaging to the device, provided that it is limited to 5 ma or less. for the op284, once the input exceeds the negative supply by 0.6 v, the input current quickly exceeds 5 ma. if this condition continues to exist, an external series resistor should be added at the expense of addi - tional thermal noise. figure 47 illustrates a typical noninverting configuration for an overvoltage - protected amplifier where the series resistance, r s , is chosen such that ( ) ma5 supply max in s vv r ? = for example, a 1 k resistor protects the op284 against input signals up to 5 v above and below the supplies. for other configu - rations where both inputs are used, each input should be protected against abuse with a series resistor. again, to ensure optimum dc and ac perfor mance, it is recommended that source impedance levels be balanced . r1 r2 v in v out 1/2 op284 00293-047 figure 47 . resistance in series with input limits overvoltage currents to safe values output phase reversa l some operational amplifiers designed for single - suppl y operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common - mode range. typically, for single- supply bipolar op amps, the negative supply determines the lower limit of their common - mode range. with these dev ices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excurs ions from exceeding the negative supply of the device (that is, gnd), preventing a condition that causes the output voltage to cha nge p hase. jfet - input amplifiers can also exhibit phase reversal; and, if so, a series input resistor is usually required to prevent it. the op284 is free from reasonable input voltage range restrictions, provided that input voltages no greater than the su pply voltages are applied. although device output does not change phase, large currents can flow through the input protection diodes , as shown in figure 46 . therefore, the technique recommended in the inp ut overvoltage protection section should be applied to those appli - cations where the likelihood of input voltages exceeding the supply voltages is high. designing low noise circuits in single - supply applications in single - supply applications, devices like the op284 extend the dynamic range of the application through the use of rail - to - rail operation. in fact, the opx84 family is the first of its kind to combine single - supply, rail - to - rail operation , and low noise in one device. it is the first device in th e industry to exhibit an input noise voltage spectral density of less than 4 nv/ hz at 1 khz. it was also designed specifically for low - noise, single -supply applications, and as such, some discussion on circuit noise concepts in single - supply applications is appropriate. referring to the op amp noise model circuit configuration illus trated in figure 48, t he expression for an amplifiers total equivalent input noise voltage for a source resistance level, r s , is given by [ ] 2 2 2 )() ()(2 noa s noa nr nt e e e ri ++ = , units in hz v where: r s = 2 r is the effective, or equivalent, circuit source resistance. (e nr ) 2 is the source resistance thermal noise voltage power (4 ktr) . k is the boltzmanns constant = 1.38 10 C 23 j/k. t is the ambient temperature in kelvins of the circuit = 273.15 + t a (c). ( i noa ) 2 is the op am p equivalent input noise current spectral power (1 hz bandwidth ). ( e noa ) 2 is the op amp equivalent input noise voltage spectral power (1 hz bandwidth). e nr e nr e noa i noa i noa r noiseless r noiseless 00293-048 ideal noiseless op amp r s = 2r figure 48 . op amp noise circuit model used to determine total circuit equival ent input noise voltage and noise figure
op184/op284/op484 rev. j | page 16 of 24 as a design aid, figure 49 shows the total equivalent input noise of the op284 and the total thermal noise of a resistor for com - parison. note that for sourc e resistance less than 1 k , the equivalent input noise voltage of the op284 is dominant. total source resistance, r s (?) 100 1 equivalent thermal noise (nv/ hz) 10 10k op284 total equivalent noise resistor thermal noise only 00293-049 100 1k 100k frequency = 1khz t a = 25c figure 49 . op284 equivalent thermal noise vs. total source resistance because c ircuit snr is the critical parameter in the final analysis, the noise behavior of a circuit is often expressed in terms of its noise figure, nf. the noise figure is defined as the ratio of a circuits output signal - to - nois e to its input signal - to - noise. an expression of a circuit nf in db, and in terms of the opera tional amplifier voltage and current noise parameters defined previously, is given by u 2 2 2 1log10 db nrs s noa noa e rie nf where: nf ( db ) is the noise figure of the circuit, expressed in decibels . ( e noa ) 2 is the op284 noise voltage spectral power (1 hz bandwidth ). ( i n oa ) 2 is the op284 noise c urrent spectral power (1 hz bandwidth ). ( e nrs ) 2 is the source resistance thermal noise voltage power = (4ktr s ). r s is the effective, or equivalent, source resistance presented to the amplifier. calculation of the c ircuit noise figu re is straightforward b ecause the signal level in the application is not required to determine it. however, many designers using nf calculations as the basis for achieving optimum snr believe that a low noise figure is equal to low total noise. in fact, th e opposite is true, as shown in figure 50. t he n oise figure of the op284 is expressed as a function of the s ource resistance level. note that the lowest noise figure for the op284 occurs at a source resistance level of 10 k . however, figure 49 shows that this source resistance level and the op284 generate approximately 14 nv/ hz of total equivalent circuit noise. signal levels in the application invariably increase to maximize circuit snr, which is not an option in low voltage, single - supply applications. total source resistance, r s (?) 10 100 noise figure (db) 5 10k 100k 1k 0 9 8 7 6 4 3 2 1 00293-050 frequency = 1khz t a = 25c figure 50 . op284 noise figure vs. source resistance t herefore, to achieve optimum circuit snr in single -supply applications, it is recommended that an operational amplifie r with the lowest equivalent input noise voltage be chosen, along with source resistance levels that are consistent with maintaining low total circuit noise. overdrive recovery the overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. the recovery time is important in applications where the amplifi er must recover quickly after a large transient event. the circuit shown in figure 51 was used to evaluate the op284 overload recovery time. the op284 takes approximately 2 s to recover from positive saturation and approximately 1 s to recover from negative saturation. 2 3 1 +5v 8 4 r1 10k? r3 9k? r2 10k? v in 10v step ?5v v out 1/2 op284 00293-051 figure 51 . output overload recovery test circuit single - supply, 3 v instrume ntation amplifier the low noise, wide bandwidth, and rail - to - rail input/output operation of the op284 make it ideal for low supply voltage applications such as in the two op amp instrumentation amplifier shown in figure 52 . the circuit uses the classic two op amp instrumentation amplifier topology with four resistors to set the gain. the transfer equation of the circuit is identical to that of a noninverting amplifier. resistor r2 and resistor r3 should be closely matched to each other, as well as to resistors (r1 + p1) and resistor r4 to ensure good common - mode rejection performance.
op184/op284/op484 rev. j | page 17 of 24 resistor networks should be used in this circuit for r2 and r3 because they exhibit the necessary relative to lerance matching for good performance. matched networks also exhibit tight rela tive resistor temperature coefficients for good circuit temperature stability. trimming potentiometer p1 is used for optimum dc cmr adjustment, and c1 is used to optimize ac cmr . with the circuit values as shown, circuit cmr is better than 80 db over the frequency range of 20 hz to 20 khz. circuit referred - to - input (rti) noise in the 0.1 hz to 10 hz band is an impressively low 0.45 v p - p. resistor rp1 and resistor rp2 serve to p rotect the op284 inputs against input overvoltage abuse. capacitor c2 can be included to the limit circuit bandwidth and, t herefore, wide bandwidth noise in sensitive applications. the value of this capacitor should be adjusted , depending on the re quired c losed - loop bandwidth of the circuit. the r4 to c2 time constant creates a pole at a frequency equal to ( ) 242 1 3 cr db f = 2.5 v reference from a 3 v supply in many single - supply applications, the need for a 2.5 v reference often arises. many commercia lly available monolithic 2.5 v references require at least a minimum operating supply of 4 v. the problem is exacerbated when the minimum operating supply voltage is 3 v. the circuit illustrated in figure 53 is an example of a 2. 5 v reference that operates from a single 3 v supply. the circuit takes advantage of the op284 rail - to - rail input/output voltage ranges to amplify an ad589 1.235 v output to 2.5 v. 00293-052 v out 5 6 7 3v a1, a2 = 1/2 op284 gain = 1 + r4 r3 set r2 = r3 r1 + p1 = r4 8 4 c2 rp1 1k? rp2 1k? r1 9.53k ? r2 1.1k ? r3 1.1k ? r4 10k? p1 500? 3 2 1 v in a1 + ? a2 c1 ac cmrr trim 5pf to 40pf figure 52 . single supply, 3 v low noise instrumentation amplifier the low tcv os of the op284 at 1.5 v/c helps maintain an output voltage temperature coefficient that is dominated by the temperature coefficients of r2 an d r3. in this circuit with 100 ppm/c t cr resistors, the output voltage exhibits a tempera - ture coefficient of 200 ppm/c. lower tempco resistors are recommended for more accurate performance over temperature. one measure of the performance of a voltage reference is its capacity to recover fro m sudden changes in load current. while sourcing a steady - state load current of 1 ma, this circuit recovers to 0.01% of the programmed output voltage in 1.5 s for a total change in load current of 1 ma. 00293-053 2.5v ref 3 2 1 3v 8 4 r3 100k? r2 100k? p1 5k? r1 17.4k ? 3v 0.1f ad589 1/2 op284 + ? resistors = 1%, 100ppm/c potentiometer = 10 turn, 100ppm/c figure 53 . 2.5 v reference that operates on a single 3 v supply 5 v only, 12 - bit dac swings rail - to - rail the op284 is ideal for use with a cmos dac to generate a digitally controlle d voltage with a wide output range. figure 54 shows a dac8043 used in conjunction with the ad589 to gen - erate a voltage output from 0 v to 1.23 v. the dac is actually operating in voltage switching mode, where the reference is co nnected to the current output, i out , and the output voltage is taken from the v ref pin. this topology is inherently noninverting, as opposed to the classic current output mode, which is inverting and not usable in single - supply applications. 3 2 1 5v 5v 8 4 r3 232? 1% r2 32.4 ? 1% r1 17.8k ? r4 100k? 1% ad589 gnd clk sr1 ld v ref r rb v dd i out 1.23v 4 8 2 1 3 dac8043 digital control 7 6 5 1/2 op284 v out = d 4096 (5v) 00293-054 figure 54 . 5 v only, 12 - bit dac swings rail -to- rail in this application , the op284 serves two functions. first, it buffers the hi gh output impedance of the dac v ref pin, which is on the order of 10 k . the op amp provides a low impedance outpu t to drive any following circuitry. second, the op amp amplifies the output signal to provide a rail - to - rail output swing. in this particular case, the gain is set to 4.1 so that the circuit generates a 5 v output when the dac output is at full scale. if other output voltage ranges are needed, such as 0 v v out 4.095 v, the gain can be easily changed by adjusting the values of r2 and r3.
op184/op284/op484 rev. j | page 18 of 24 high - side current monitor in the design of power supply control circuits, a great deal of design effort is focused on ensuring the long - term reliability of a pass tran sistor over a wide range of load current conditions. as a result, monitoring and limiting device power dissipation is of prime importance in these designs. the circuit shown in figure 55 is an example of a 3 v, single - supply, h igh - side current monitor that can be incorporated into the design of a voltage regulator with fold - back current limiting or a high current power supply with crowbar protection. this design uses an op284 rail - to - rail input voltage range to sense the voltage drop across a 0.1 current shunt. a p - channel mosfet , used as the feedback element in the circuit , converts the differential input voltage of the op amp into a current. this current is applied to r2 to generate a voltage that is a linear representation o f the load current. the transfer equation for the current monitor is given by monitor output = l sense i r1 r r2 ? ? ? ? ? ? for the element values shown, the transfer characteristic of the monitor output is 2.5 v/a. 00293-055 r sense 0.1 ? i l 8 1 4 3 3v 3v g s d 2 m1 si9433 monitor output 3v 1/2 op284 r1 100? r2 2.49k ? 0.1f figure 55 . high - si de load current monitor capacitive load drive capability the op284 exhibits excellent capacitive load driving capabilities. it can drive up to 1 nf, as shown in figure 30 . even though the device is stable, a capacitive load does not come without penalty in bandwidth. the bandwidth is reduced to less than 1 mhz for loads greater than 2 nf. a snubber network on the output does not increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive load. a snubber consists of a series r - c network (r s , c s ), as shown in figure 56 , connected from the output of the device to ground. this network operates in parallel with the load capacitor, c l , to provide the necessary phase lag compensation. the value of the resistor and capacitor is best determined empirically. 00293-056 r s 50? 0.1f c l 1nf c s 100nf 5v v in 100mv p-p v out 1/2 op284 figure 56 . snubber network compensates for capacitive load the first step is to determine the value of resistor r s . a good starting value i s 10 0 (typically, the optimum value is less than 100 ). this value is reduced until the small - signal transient response is optimized. next, c s is determined; 10 f is a good starting point. this value is reduced to the smallest value for acceptable performance (typically, 1 f). for the case of a 10 nf load capacitor on the op284, the optimal snubber network is a 20 in series with 1 f. the benefit is immediately apparent, as shown in the scope photo in figure 57 . the top trac e was taken with a 1 nf load, and the bottom trace was taken with the 50 , 100 nf snubber network in place. the amount of over shoot and ringing is dramatically reduced. table 7 shows a few sample snubber networks for large load capacitors. 00293-057 2s 100 90 10 0% 50mv 1nf load only snubber in circuit dly 5.49s 50mv b w figure 57 . overshoot and ringing are reduced by adding a snubber network in parallel with the 1 nf load table 7 . snubber networks for large capacitive loads load capacitance (c l ) snubber netwo rk (r s , c s ) 1 nf 50 ?, 100 nf 10 nf 20 ?, 1 f 100 nf 5 ?, 10 f
op184/op284/op484 rev. j | page 19 of 24 low dropout regulato r with current limiting many circuits require stable, regulated voltages relatively close in potential to an unregulated input source. this low dropout type of regulator is re adily implemented with a rail - to - rail output op amp, such as the op284, because the wide output swing allows e asy drive to a low saturation voltage pass device. furthermore, it is particularly useful when the op amp also employs a rail - to - rail input featur e because this factor allows it to perform high - side current sensing for positive rail current limiting. typical examples are voltages developed from 3 v to 9 v range system sources or anywhere that low dropout performance is required for power efficiency. this 4.5 v example works from 5 v nominal sources with worst - case levels down to 4.6 v or less. figure 58 shows such a regulator set up, using an op284 plus a low r ds(on) , p- channel mosfet pass device. part of the low dropout pe rform - a nce of this circuit is provided by q1, which has a rating of 0.11 with a gate drive voltage of only 2.7 v. this relatively low gate drive threshold allows operation of the regulator on supplies as low as 3 v without compromising overall performance. the main voltage control loop operation of the circuit is provided by u1b, half of the op284. this voltage control amplifier amplifies the 2.5 v reference voltage produced by three terminal u2, a ref192. the regulated output voltage, v out , is then ? ? ? ? ? ? += 3 1 r r2 vv 2 out out for this example, because v out of 4.5 v with v out2 = 2.5 v requires a u1b gain of 1.8 times, r3 and r2 are chosen for a ratio of 1.2:1 or 10.0 k :8.06 k (using closest 1% values). note that for the lowest v out dc error, r2||r3 should be maintained equal to r1 (as in this example), and the r2 to r3 resistors should be stable, close tolerance metal film types. the table in figure 58 summarizes r1 to r3 values for some popular voltages. however, note that, in general, the output can be anywhere between v out2 and the 12 v maximum rating of q1. while the low voltage saturation characteristic of q1 is a key part of the l ow dropout, another component is a low current sense com - parison threshold with good dc accuracy. here, this is provided by current sense amplifier u1a, which is provided by a 20 mv reference from the 1.235 v, ad5 89 reference diode d2, and the r7 to r8 divider. when the product of the output current and the r s value match this voltage threshold, the current control loop is activated, and u1a drives the q1 gate through d1. this causes the overall circuit operation to enter current mode control with a current limit, i limit , defined as ( ) ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = r8r r7 r v i s d2r limit 7 3 2 1 8 4 u1a op284 u1b op284 d2 ad589 d1 1n4148 q1 si9433dy 6 5 7 d3 1n4148 2 6 4 3 u2 ref192 r3 10k? v c v in common +v s v s > v out + 0.1v c4 0.1f c5 0.01f c2 1f c1 0.01f c6 10f v out common v out = 4.5v @ 350ma (see table) c2 0.1f optional on/off control input cmos hi (or open) = on lo = off v out r1k? r2k? r3k? output table 5.0v 4.99 10.0 10.0 4.5v 4.53 8.08 10.0 3.3v 2.43 3.24 10.0 3.0v 1.69 2.00 10.0 r5 22.1k ? r4 2.21k ? r6 4.99k ? r9 27.4k ? r11 1k? r10 1k? r1 4.53k ? v out2 2.5v r7 4.99k ? r8 301k? r2 8.06k ? r s 0.05 ? 00293-058 figure 58 . low dropout regulator with current limiting \
op184/op284/op484 rev. j | page 20 of 24 obviously, it is desirable to keep this comparison voltage small becaus e it becomes a significant portion of the overall dropout voltage. here, the 20 mv reference is higher than the typical offset of the op284 but is still reasonably low as a percentage of v out (<0.5%). in adapting the limiter for other i limit levels, sense resistor r s should be adjusted along with r7 to r8, to maintain this threshold voltage between 20 mv and 50 mv. performance of the circuit is excellent. for the 4.5 v output version, the measured dc output change for a 225 ma load change was on the order of a few micro volts, while the dropout voltage at this same current level was about 30 mv. the current limit, as shown in figure 58 , is 400 ma, allowing the circuit to be used at levels up to 300 ma or more. while the q1 device c an actually support currents of several amperes, a practical current rating takes into account the 2.5 w, 25 c dissipation of the 8- lead soic device. because a short - circuit current of 400 ma at an input level of 5 v causes a 2 w dissipation in q1, other input conditions must be considered carefully in terms of potential overheating of q1. of course, if higher powered devices are used for q1, this circuit can support outputs of tens of amperes as well as the higher v out levels already noted. the circuit sh own can either be used as a standard low dropout regulator, or it can be used with on/off control. by driving pin 3 of u 2 with the optional logic control signal, v c , the output is switched between on and off. note that when the output is off in this circui t, it is still active (that is, not an open circuit). this is because the off state simply reduces the voltage input to r1, leaving the u1a/u1b amplifiers and q1 still active. when the on/off control is used, resistor r10 should be used with u 2 to speed o n/off switching and to allow the output of the circuit to settle to a nominal zero voltage. component d3 and component r11 also aid in speeding up the on/off transition by providing a dynamic discharge path for c2. off/on transition time is less than 1 ms, while the on/off transition is longer, but less than 10 ms. 3 v, 50 hz/60 hz act ive notch filter wit h false ground to process signals in a single - supply system, it is often best to use a false ground biasing scheme. a circuit that uses this approach is sh own in figure 59 . in this circuit, a false ground circuit biases an active notch filter used to reject 50 hz/60 hz power line interference in portable patient monitoring equipment. notch filters are commonly used to reject powe r line frequency interference that often obscures low frequency physiological signals, such as heart rates, blood pressure readings, eegs, and ekgs. this notch filter effectively squelches 60 hz pickup at a filter q of 0.75. substituting 3.16 k resistors for the 2.67 k resistor in the t win - t section (r1 through r5) configures the active filter to reject 50 hz interference. 00293-059 r2 2.67k ? r6 10k? r7 1k? r8 1k? r11 10k? r9 20k? r12 150? r10 20k? 1 3 5 6 7 11 2 3v v o v in a2 a1 8 a3 4 10 9 3v a1, a2, a3 = op484 q = 0.75 note: for 50hz applications change r1, r2, r3, and r4 to 3.1k ? and r5 to 1.58k ? (3.16k? 2). r3 2.67k ? r1 2.67k ? r4 2.67k ? r5 1.33k ? (2.68k ? 2) c3 2f (1f 2) c5 0.03f c1 1f c2 1f c4 1f c6 1f 1.5v figure 59 . a 3 v single - supply, 50hz to 60 hz active notch filter with false ground amplifier a3 is the h eart of the false ground bias circuit. it buffers the voltage developed at r9 and r10 and is the reference for the active notch filter. because the op484 exhibits a rail - to - rail input common - mode range, r9 and r10 are chosen to split the 3 v supply symmetr ically. an in - the - loop compensation scheme is used around the op484 that allows the op amp to drive c6, a 1 f capacitor, without oscillation. c6 maintains a low impedance ac ground over the operating frequency range of the filter. the filter section uses an op484 in a twin - t configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin - t section. mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the pass band symmetry of the filter. using 1% resistors and 5% capacitors produce s satis - factory results.
op184/op284/op484 rev. j | page 21 of 24 outline dimensions compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equi v alents for reference on ly and are not appropri a te for use in design. corner leads m ay be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) sea ting plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 60 . 8 - lead plastic dual in - line package [pdip] (n- 8) p- suffix dimensions shown in inches and (millimeters) compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equi v alents for reference on ly and are not appropri a te for use in design. corner leads m ay be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 10 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max sea ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) figure 61 . 14 - lead plastic dual in - lin e package [pdip] (n- 14) p- suffix dimensions shown in inches and (millimeters)
op184/op284/op484 rev. j | page 22 of 24 controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equivalents for reference onl y and are not appropriate for use in d esign. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 62 . 8 - lead standard small outline package [soic_n] narrow body (r- 8) s- suffix dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equi v alents for reference on ly and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 63 . 14 - lead standard small outline package [soic_n] narrow body (r- 14) s- suffix dimensions shown in millimeters and (inches)
op184/op284/op484 rev. j | page 23 of 24 ordering guide model 1 temperature range package description package option op184es ? 40c to +125c 8- lead soic_n s- suffix ( r-8) op184es - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184es - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184esz ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184esz - reel ? 40c to +125 c 8- lead soic_n s- suffix (r-8) op184esz - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184fs ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184fs - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184fs C reel7 ? 40c to +125c 8- lead so ic_n s- suffix (r-8) op184fsz ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184fsz - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op184fsz - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284ep ? 40c to +125c 8- lead pdip p- suffix (n -8) op284epz ? 40c to +125c 8- lead pdip p- suffix (n -8) op284es ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284es - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284es - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284esz ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284esz - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284esz - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284fs ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284fs - reel ? 40c to +125 c 8- lead soic_n s- suffix (r-8) op284fs - reel7 ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284fsz ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284fsz - reel ? 40c to +125c 8- lead soic_n s- suffix (r-8) op284fsz - reel7 ? 40c to +125c 8- lead so ic_n s- suffix (r-8) op484es ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484es - reel ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484esz ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484esz - reel ? 40c to +125c 14- lead soic_n s- suf fix (r - 14) op484fpz ? 40c to +125c 14- lead pdip p- suffix (n -14) op484fs ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484fs - reel ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484fs - reel7 ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op 484fsz ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484fsz - reel ? 40c to +125c 14- lead soic_n s- suffix (r- 14) op484fsz - reel7 ? 40c to +125c 14- lead soic_n s- suffix (r- 14) 1 z = rohs compliant part .
op184/op284/op484 rev. j | page 24 of 24 notes ? 1996 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00293 -0- 4/11( j )

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